ELEC ENG 2100 - Digital Systems
North Terrace Campus - Semester 2 - 2024
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General Course Information
Course Details
Course Code ELEC ENG 2100 Course Digital Systems Coordinating Unit Electrical and Electronic Engineering Term Semester 2 Level Undergraduate Location/s North Terrace Campus Units 3 Contact Typically up to 2 hours per week but up to 5 hours in the weeks with practicals Available for Study Abroad and Exchange Y Prerequisites ELEC ENG 1102 Incompatible ELEC ENG 3028 Assessment Workshop Preparation, Tests, Exam Course Staff
Course Coordinator: Dr Xin Yuan (Vernon)
Course Timetable
The full timetable of all activities for this course can be accessed from .
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Learning Outcomes
Course Learning Outcomes
On successful completion of this course students will be able to:
1 Design, build and test digital logic for systems of moderate complexity using common digital components, schematic diagrams, and hardware description language 2 Use and explain engineering practices to manage the complexity of digital systems 3 Use appropriate implementation technologies for digital systems 4 Design CMOS logic gates at the transistor schematic level 5 Work effectively and ethically in teams to undertake the design of digital systems
The above course learning outcomes are aligned with the Engineers Australia . The course develops the following EA Elements of Competency to levels of introductory (A), intermediate (B), advanced (C):
1.1 1.2 1.3 1.4 1.5 1.6 2.1 2.2 2.3 2.4 3.1 3.2 3.3 3.4 3.5 3.6 B C C A B — B C B B — B — B B B University Graduate Attributes
This course will provide students with an opportunity to develop the Graduate Attribute(s) specified below:
University Graduate Attribute Course Learning Outcome(s) Attribute 1: Deep discipline knowledge and intellectual breadth
Graduates have comprehensive knowledge and understanding of their subject area, the ability to engage with different traditions of thought, and the ability to apply their knowledge in practice including in multi-disciplinary or multi-professional contexts.
1-5 Attribute 2: Creative and critical thinking, and problem solving
Graduates are effective problems-solvers, able to apply critical, creative and evidence-based thinking to conceive innovative responses to future challenges.
1-5 Attribute 3: Teamwork and communication skills
Graduates convey ideas and information effectively to a range of audiences for a variety of purposes and contribute in a positive and collaborative manner to achieving common goals.
2, 5 Attribute 4: Professionalism and leadership readiness
Graduates engage in professional behaviour and have the potential to be entrepreneurial and take leadership roles in their chosen occupations or careers and communities.
2, 5 Attribute 5: Intercultural and ethical competency
Graduates are responsible and effective global citizens whose personal values and practices are consistent with their roles as responsible members of society.
5 Attribute 7: Digital capabilities
Graduates are well prepared for living, learning and working in a digital society.
1-5 Attribute 8: Self-awareness and emotional intelligence
Graduates are self-aware and reflective; they are flexible and resilient and have the capacity to accept and give constructive feedback; they act with integrity and take responsibility for their actions.
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Learning Resources
Required Resources
Textbook: David Harris and Sarah Harris, Digital Design and Computer Architecture, Elsevier, Second Edition (2013). The full text of this book is available electronically from the 成人大片 Library.
A set of slides, recorded slide show presentations, practice problems, worked solutions, and other supporting materials will be available for downloading from the course web site.Online Learning
This course uses the MyUni website. All announcements are posted on MyUni. Recorded slide show presentations, practice and workshop questions, and other resources are available on MyUni. The gradebook is used to communicate marks. The SystemVerilog assignment is submitted using MyUni. A discussion board is available for course-related discussion. -
Learning & Teaching Activities
Learning & Teaching Modes
Workshops: the course uses a flipped classroom with an emphasis on weekly 3-hour face-to-face workshops. Students prepare for workshops by reading sections of the textbook, watching recorded presentations, and attempting preparation exercises. During workshops, teaching staff spend time with each student individually to help explain difficult concepts. Workshop time is also spent working as individuals on exercise problems and in small groups on design problems.
Recorded Presentations: wherever possible the presentations follow the structure, terminology and notation of the course textbook. Slides and recoded presentations are available prior to workshops and, where material outside of the scope of the textbook is presented, detailed notes are provided. Students are expected to read sections of the textbook, watch the presentations and attempt some exercise problems in preparation for workshops.Workload
The information below is provided as a guide to assist students in engaging appropriately with the course requirements.
The information below is provided as a guide to help students engage appropriately with the course requirements.
Activity Contact Hours Workload Hours Workshop Preparation 36 Recorded Slide Presentations 36 Tests 3 12 Workshops 36 36 Practice Questions and Revision 24 Assignment 6 Total 39 150
Learning Activities Summary
Week Workshop Topic Assignment Test 1 Topic 1: Building Digital Systems 2 Topic 1: Building Digital Systems 3 Topic 2: Combinational Logic Design 4 Topic 2: Combinational Logic Design Test 1 5 Topic 3: Sequential Logic Design 6 Topic 3: Sequential Logic Design 7 Topic 4: CMOS Logic Test 2 8 Topic 4: CMOS Logic 9 Topic 5: Digital Subsystems & Interfaces 10 Topic 5: Digital Subsystems & Interfaces Test 3 11 Review and Integration SystemVerilog assignment 12 Review and Integration -
Assessment
The University's policy on Assessment for Coursework Programs is based on the following four principles:
- Assessment must encourage and reinforce learning.
- Assessment must enable robust and fair judgements about student performance.
- Assessment practices must be fair and equitable to students and give them the opportunity to demonstrate what they have learned.
- Assessment must maintain academic standards.
Assessment Summary
Assessment Task Weighting (%) Individual/ Group Formative/ Summative Due (week)* Hurdle criteria Learning outcomes Workshops (12) 12 Individual Formative Weeks 1-12 1-5 Mid-semester tests (3) 24 Individual Summative Weeks 4, 7, 10 1-4 Assignment 8 Individual Summative Week 11 1-4 Exam 56 Individual Summative Min 40% 1-4 Total 100
This assessment breakdown is registered as an exemption to the University's . The exemption is related to the Procedures clause(s): 1. b. 3.Assessment Detail
Workshops: students maintain an exercise book in which they record workshop preparation and the work completed during workshops. This is assessed during workshops on the basis of the student having attempted and then corrected prescribed exercises.
Tests: tests are held online in weeks 4, 7 and 10.
Assignment: an individual SystemVerilog assignment.
Exam: a 2-hour examination is held at the end of the semester. The final exam is a hurdle requirement. Students must achieve a grade of at least 40% on their final exam assessment or their mark will be capped at 49F.
Students must achieve an overall final mark of 50% to pass.
Submission
Workshops: exercise books are marked during the workshops. Marks are awarded for completion of the previous workshop and preparation for the current one.
Tests: tests are completed online in MyUni during the scheduled hour shown in Access Adelaide for weeks 4, 7, and 10.
Assignment: the assignment is required to be submitted online with the SystemVerilog code and a short video to demonstrate the functionality of the program.
Exam: the exam is conduced as part of the University scheduled and facilitated exams at the end of semster.
Extensions for workshops and tests can be arranged for circumstances eligible for modified arrangements under the Modified Arrangements for Coursework Assessment Policy. Please contact the Course Coordinator or to request an extension.Course Grading
Grades for your performance in this course will be awarded in accordance with the following scheme:
M10 (Coursework Mark Scheme) Grade Mark Description FNS Fail No Submission F 1-49 Fail P 50-64 Pass C 65-74 Credit D 75-84 Distinction HD 85-100 High Distinction CN Continuing NFE No Formal Examination RP Result Pending Further details of the grades/results can be obtained from Examinations.
Grade Descriptors are available which provide a general guide to the standard of work that is expected at each grade level. More information at Assessment for Coursework Programs.
Final results for this course will be made available through .
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Student Feedback
The University places a high priority on approaches to learning and teaching that enhance the student experience. Feedback is sought from students in a variety of ways including on-going engagement with staff, the use of online discussion boards and the use of Student Experience of Learning and Teaching (SELT) surveys as well as GOS surveys and Program reviews.
SELTs are an important source of information to inform individual teaching practice, decisions about teaching duties, and course and program curriculum design. They enable the University to assess how effectively its learning environments and teaching practices facilitate student engagement and learning outcomes. Under the current SELT Policy (http://www.adelaide.edu.au/policies/101/) course SELTs are mandated and must be conducted at the conclusion of each term/semester/trimester for every course offering. Feedback on issues raised through course SELT surveys is made available to enrolled students through various resources (e.g. MyUni). In addition aggregated course SELT data is available.
The following changes have been made for 2024 in response to last year's feedback
- changed one of the workshops to be a special SystemVerilog review
- the activities of one of the workshops, which have typically taken much longer than the others, will be submitted as an assignment so that it receives extra weight in the assessment. The exam weight has been reduced.
- reduced the focus of SystemVerilog assessment in the tests, given it will be covered in the new assignment.
- moved to 3-hour flexible workshops.
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Student Support
- Academic Integrity for Students
- Academic Support with Maths
- Academic Support with writing and study skills
- Careers Services
- Library Services for Students
- LinkedIn Learning
- Student Life Counselling Support - Personal counselling for issues affecting study
- Students with a Disability - Alternative academic arrangements
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Policies & Guidelines
This section contains links to relevant assessment-related policies and guidelines - all university policies.
- Academic Credit Arrangements Policy
- Academic Integrity Policy
- Academic Progress by Coursework Students Policy
- Assessment for Coursework Programs Policy
- Copyright Compliance Policy
- Coursework Academic Programs Policy
- Intellectual Property Policy
- IT Acceptable Use and Security Policy
- Modified Arrangements for Coursework Assessment Policy
- Reasonable Adjustments to Learning, Teaching & Assessment for Students with a Disability Policy
- Student Experience of Learning and Teaching Policy
- Student Grievance Resolution Process
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