ELEC ENG 4053 - Digital Microelectronics

North Terrace Campus - Semester 1 - 2016

Introduction to fabrication processes; Design rules (revisited); Transistor models (revisited from third year electronics); Layout issues; ASIC design flow; VLSI design methodology and leaf cell design; Performance estimation of CMOS complex gates and interconnected modules using logical effort; Interconnect types and issues, clock distribution, design margin, reliability and scaling; Static and dynamic CMOS logic families and adders design; Memories-static and dynamic RAMS, Pseudon-NMOS and dynamic PLA; Low power design and system level consideration.

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Course Details

Course Code	ELEC ENG 4053
Course	Digital Microelectronics
Coordinating Unit	School of Electrical & Electronic Engineering
Term	Semester 1
Level	Undergraduate
Location/s	North Terrace Campus
Units	3
Contact	up to 6 hours per week
Available for Study Abroad and Exchange	Y
Incompatible	ELEC ENG 4037
Assumed Knowledge	ELEC ENG 2008, ELEC ENG 2011, ELEC ENG 3028
Assessment	Written exam, test, computer labs and project work

Course Staff

Course Coordinator: Dr Said Al-Sarawi

Course Coordinator and Lecturer: Dr Said Al-Sarawi
Email: said.alsarawi@adelaide.edu.au
Office: Ingkarni Wardli 3.39
Phone: 8313 4198

Course Timetable

The full timetable of all activities for this course can be accessed from .

Course Learning Outcomes

At the end of this course, students are expected to:

Understand the characteristics of CMOS technology and the process of CMOS fabrication to a sufficient level to appreciate the implications of layout and technology on circuit behaviour.
Be able to design digital logic gates at transistor schematic and layout level for implementation in CMOS technology.
Understand the parasitic effects and loading on CMOS circuit performance.
Understand contemporary CMOS design methodologies.
Be able to design leaf cells for standard-cell and full-custom projects.
Be able to estimate complementary CMOS circuit performance, size and noise margin.
Be able to minimise the delay of a combinatorial logic circuit implemented in complementary CMOS technology.
Be able to model the effect of interconnect upon a design and to apply strategies to mitigate problems arising from interconnect loading.
Be able to explain the function of CMOS memory circuits and design basic CMOS ROM and PLA circuits.
Understand factors that influence circuit reliability and be able to apply reasonable design margins.
Understand the effect of scaling on circuit behaviour and appreciate technology trends with respect to scaling.
Be able to design circuits using complementary CMOS, pseudo-nMOS, pass transistor, footed and footless domino logic families.
Understand the importance of system level considerations such as floor planning, power dissipation, clock skew and micro-architecture to system performance.
Appreciate current challenges in microelectronic circuit design.
Be aware of alternative process technologies, their benefits, drawbacks and potential applications.
Be able to use a set of software tools to specify, synthesise, layout and simulate microelectronic circuits.
Ability to work as part of a team to design a system module

University Graduate Attributes

This course will provide students with an opportunity to develop the Graduate Attribute(s) specified below:

University Graduate Attribute	Course Learning Outcome(s)
Deep discipline knowledge informed and infused by cutting edge research, scaffolded throughout their program of studies acquired from personal interaction with research active educators, from year 1 accredited or validated against national or international standards (for relevant programs)	All
Critical thinking and problem solving steeped in research methods and rigor based on empirical evidence and the scientific approach to knowledge development demonstrated through appropriate and relevant assessment	4,6,7,9,10,13-15
Teamwork and communication skills developed from, with, and via the SGDE honed through assessment and practice throughout the program of studies encouraged and valued in all aspects of learning	15-17
Career and leadership readiness technology savvy professional and, where relevant, fully accredited forward thinking and well informed tested and validated by work based experiences	1-7, 12-14

Learning Resources

Required Resources

Textbook
Neil H. E. Weste & David Harris, “CMOS VLSI design: a circuits and systems perspective,” Addison Wesley, 3rd edition, 2004.

Reference Books
Rabaey, Chandrakasan & Nikolil, “Digital Integrated Circuits,” Prentice Hall, 2nd edition, 2003.

A set of course notes, practice problems and other supporting materials will also be available for downloading from the course web site.

Online Learning

Extensive use will be made of the MyUni web site for this course,

Course notes, tutorial problems and solutions, laboratory exercises and practice problems will all be available for downloading from the web site. Where the lecture theatre facilities permit, audio or video recordings of lectures will also be available for downloading.

Learning & Teaching Modes

This course relies on lectures as the primary delivery mechanism for the material. Tutorials supplement the lectures by providing exercises and example problems to enhance the understanding obtained through lectures. Practicals are used to provide hands-on experience for students to reinforce the theoretical concepts encountered in lectures. Continuous assessment activities provide the formative assessment opportunities for students to gauge their progress and understanding.

Workload

The information below is provided as a guide to assist students in engaging appropriately with the course requirements.

Activity		Contact Hours	Workload Hours
Lecture	24 Lectures	24	48
Tutorials	5 Tutorials	5	10
Practicals	Computer Lab 1	3	6
	Computer Lab 2	3	8
	Computer Lab 3	3	8
	Computer Lab 4	6	12
Test	Theory part of the course	1	6
Exam (undergrad)	All theory part	1.5	14
		46.5	112

Learning Activities Summary

Lectures Activity	Session No.	Week	No. of Lectures
Introduction to the course and presentation of prac structure	1&2	1	2
Introduction to fabrication processes, design rules (revisited), Transistor models (revisited from third year electronics) and Layout issues and ASIC design flow	2&3	2	2
VLSI design methodology and leaf cell design	4&5	3	2
Performance estimation of CMOS complex gates and interconnected modules using logical effort	6-13	4-7	8
Interconnect issues, clock distribution, design margin, reliability and scaling	14-17	8&9	4
Static and dynamic CMOS logic families and adders design	18-20	10&11	2
Memory structures and operation	21&22	11&12	2
Low power design and system level consideration	23&24	12	2

Tutorials Activity	Sessions	Week	Topic
Demonstrating the design of complex CMOS gates and transistor sizing.	1	4	Tutorial 1
CMOS Circuits layouts and delay estimation	2	6	Tutorial 2
CMOS circuits delay estimation using logical efforts	3	8	Tutorial 3
Delay path estimation using logical effort	4	10	Tutorial 4
Delay and crosstalk in interconnects	5	12	Tutorial 5

Practicals
Note that practical classes begin in week 1 of the semester and run in odd weeks. Students must attend their allocated practical class, when further instructions on the operation of the laboratory session will be provided. Students should be aware of the Occupational Health and Safety issues associated with working in a laboratory environment.

The University's policy on Assessment for Coursework Programs is based on the following four principles:

Assessment must encourage and reinforce learning.
Assessment must enable robust and fair judgements about student performance.
Assessment practices must be fair and equitable to students and give them the opportunity to demonstrate what they have learned.
Assessment must maintain academic standards.

Assessment Summary

Undergraduate assessment summary:

Assessment activity	Type	Weighting	Due date	Learning objective addressed
Computer Lab 1	Diagnostic	2%	Week 3	All
Computer Lab 2	Diagnostic	3%	Week 6	All
Computer Lab 3	Diagnostic	5%	Week 8	All
Test	Summative	10%	Week 11	All
Computer Lab 4	Summative	15%	Week 12	All
Exam	Summative	65%	Week 12	All

Assessment Detail

The examination is a hurdle requirement. It is necessary to achieve at least 40% in the exam. If this is not achieved, the total course mark will be limited to a maximum of 49.

A hurdle requirement is defined by the University's as "...an assessment task mandating a minimum level of performance as a condition of passing the course.
If a student fails to meet a hurdle requirement (normally no less than 40%),and is assigned a total mark for the course in the range of 45-49, then the student is entitled to an offer of additional assessment of some type. The type of assessment is to be decided by the School Assessment Review Committee when determining final results. The student’s final total mark will be entered at no more than 49% and the offer of an additional assessment will be specified eg. US01. Once the additional assessment has been completed, this mark will be included in the calculation of the total mark for the course and the better of the two results will apply. Note however that the maximum final result for a course in which a student has sat an additional assessment will be a “50 Pass”.

If a student is unable to meet a hurdle requirement related to an assessment piece (may be throughout semester or at semester’s end) due to medical or compassionate circumstances beyond their control, then the student is entitled to an offer of replacement assessment of some type. An interim result of RP will be entered for the student, and the student will be notified of the offer of a replacement assessment. Once the replacement assessment has been completed, the result of that assessment will be included in the calculation of the total mark for the course.

An assessment of work done during the lab will be conducted at the end of each lab session.

Submission

Submission will be through MyUni and information on the process will be provided for each assignment in due course.

Course Grading

Grades for your performance in this course will be awarded in accordance with the following scheme:

M10 (Coursework Mark Scheme)
Grade	Mark	Description
FNS		Fail No Submission
F	1-49	Fail
P	50-64	Pass
C	65-74	Credit
D	75-84	Distinction
HD	85-100	High Distinction
CN		Continuing
NFE		No Formal Examination
RP		Result Pending

Further details of the grades/results can be obtained from Examinations.

Grade Descriptors are available which provide a general guide to the standard of work that is expected at each grade level. More information at Assessment for Coursework Programs.

Final results for this course will be made available through .

Student Feedback

The University places a high priority on approaches to learning and teaching that enhance the student experience. Feedback is sought from students in a variety of ways including on-going engagement with staff, the use of online discussion boards and the use of Student Experience of Learning and Teaching (SELT) surveys as well as GOS surveys and Program reviews.

SELTs are an important source of information to inform individual teaching practice, decisions about teaching duties, and course and program curriculum design. They enable the University to assess how effectively its learning environments and teaching practices facilitate student engagement and learning outcomes. Under the current SELT Policy (http://www.adelaide.edu.au/policies/101/) course SELTs are mandated and must be conducted at the conclusion of each term/semester/trimester for every course offering. Feedback on issues raised through course SELT surveys is made available to enrolled students through various resources (e.g. MyUni). In addition aggregated course SELT data is available.
Student Support
Policies & Guidelines
This section contains links to relevant assessment-related policies and guidelines - all university policies.
Fraud Awareness

Students are reminded that in order to maintain the academic integrity of all programs and courses, the university has a zero-tolerance approach to students offering money or significant value goods or services to any staff member who is involved in their teaching or assessment. Students offering lecturers or tutors or professional staff anything more than a small token of appreciation is totally unacceptable, in any circumstances. Staff members are obliged to report all such incidents to their supervisor/manager, who will refer them for action under the university's student鈥檚 disciplinary procedures.

The 成人大片 is committed to regular reviews of the courses and programs it offers to students. The 成人大片 therefore reserves the right to discontinue or vary programs and courses without notice. Please read the important information contained in the disclaimer.

Authorised by:	Deputy Vice-Chancellor and Vice-President (Academic)
Maintained by:	Course Outlines Administrator

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