ELEC ENG 7051 - Digital Microelectronic Systems PG

North Terrace Campus - Semester 1 - 2024

Introduction to fabrication processes, design rules (revisited); Transistor models (revisited from third year electronics); Layout issues; ASIC design flow; VLSI design methodology and leaf cell design; Performance estimation of CMOS complex gates and interconnected modules using logical effort; Interconnect issues; Clock distribution; Design margin, reliability and scaling; Static and dynamic CMOS logic families and adders design; Memories - static and dynamic RAMS; Pseudon-NMOS and dynamic PLA; Low power design and system level consideration.

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Course Details

Course Code	ELEC ENG 7051
Course	Digital Microelectronic Systems PG
Coordinating Unit	Electrical and Electronic Engineering
Term	Semester 1
Level	Postgraduate Coursework
Location/s	North Terrace Campus
Units	3
Contact	Up to 6 hours per week
Available for Study Abroad and Exchange	Y
Incompatible	ELEC ENG 4053, ELEC ENG 3109, ELEC ENG 4109
Assumed Knowledge	Linear circuit analysis techniques, operation & characteristic of field effect transistor, binary numbers representation, digital arithmetic operation using binary system
Assessment	Written exam, test, computer labs, major project work

Course Staff

Course Coordinator: Dr Said Al-Sarawi

Course Coordinator and Lecturer: Dr Said Al-Sarawi
Email:said.alsarawi@adelaide.edu.au
Office: Ingkarni Wardli 3.39
Phone:8313 4198

Course Timetable

The full timetable of all activities for this course can be accessed from .

Course Learning Outcomes

On successful completion of this course students will be able to:

1	Explain CMOS technology fabrication and device characteristics and parasitic effects
2	Design digital logic gates and standard cells at transistor schematic and corresponding layouts level in CMOS technology using pseudo-nMOS, pass transistor, footed and footless domino logic families.
3	Explain and evaluate the effect of the parasitic and loading on CMOS circuit operation and performance in terms of size, area and noise margin and ways to minimise delay.
4	Model the effect of interconnect upon a design and to apply strategies to mitigate problems arising from interconnect loading.
5	Explain the function of CMOS memory circuits and design basic CMOS ROM and PLA circuits.
6	Explain factors that influence circuit reliability and be able to apply reasonable design margins.
7	Explain the effect of scaling on circuit behaviour and appreciate technology trends with respect to scaling.
8	Explain system level considerations such as floor planning, power dissipation, clock skew and micro-architecture to system performance.
9	Use a set of software tools to specify, synthesise, layout and simulate microelectronic circuits.
10	Demonstrate team work to design of a major digital system module

The above course learning outcomes are aligned with the Engineers Australia . The course develops the following EA Elements of Competency to levels of introductory (A), intermediate (B), advanced (C):

1.1	1.2	1.3	1.4	1.5	1.6	2.1	2.2	2.3	2.4	3.1	3.2	3.3	3.4	3.5	3.6
C	C	C	B	B	A	C	C	C	B	B	B	B	B	B	B

University Graduate Attributes

This course will provide students with an opportunity to develop the Graduate Attribute(s) specified below:

University Graduate Attribute	Course Learning Outcome(s)
Attribute 1: Deep discipline knowledge and intellectual breadth Graduates have comprehensive knowledge and understanding of their subject area, the ability to engage with different traditions of thought, and the ability to apply their knowledge in practice including in multi-disciplinary or multi-professional contexts.	1,4,6,7,8
Attribute 2: Creative and critical thinking, and problem solving Graduates are effective problems-solvers, able to apply critical, creative and evidence-based thinking to conceive innovative responses to future challenges.	2,3,5,8
Attribute 3: Teamwork and communication skills Graduates convey ideas and information effectively to a range of audiences for a variety of purposes and contribute in a positive and collaborative manner to achieving common goals.	9-10
Attribute 4: Professionalism and leadership readiness Graduates engage in professional behaviour and have the potential to be entrepreneurial and take leadership roles in their chosen occupations or careers and communities.	2,6,9,10
Attribute 5: Intercultural and ethical competency Graduates are responsible and effective global citizens whose personal values and practices are consistent with their roles as responsible members of society.	10
Attribute 8: Self-awareness and emotional intelligence Graduates are self-aware and reflective; they are flexible and resilient and have the capacity to accept and give constructive feedback; they act with integrity and take responsibility for their actions.	10

Learning Resources

Required Resources

Textbook
Neil H. E. Weste & David Harris, “CMOS VLSI design: a circuits and systems perspective,” Addison Wesley, 3rd edition, 2004.

Reference Books:
Rabaey, Chandrakasan & Nikolil, “Digital Integrated Circuits,” Prentice Hall, 2nd edition, 2003.

A set of course notes, practice problems and other supporting materials will also be available for downloading from the course web site.

Online Learning

Extensive use will be made of the MyUni web site for this course,

Course notes, tutorial problems and solutions, laboratory exercises and practice problems will all be available for downloading from the web site. Where the lecture theatre facilities permit, audio or video recordings of lectures will also be available for downloading.

Learning & Teaching Modes

This course relies on lectures as the primary delivery mechanism for the material. Tutorials supplement the lectures by providing exercises and example problems to enhance the understanding obtained through lectures. Practicals are used to provide hands-on experience for students to reinforce the theoretical concepts encountered in lectures. Continuous assessment activities provide the formative assessment opportunities for students to gauge their progress and understanding.

Workload

The information below is provided as a guide to assist students in engaging appropriately with the course requirements.

Activities		Contact Hours	Workload Hours
Lectures	24 Lectures	24	48
Tutorials	6 Tutorials	6	12
Practicals	Computer Lab 1	4	6
	Computer Lab 2	4	6
	Computer Lab 3	4	6
	Computer Lab 4	12	24
Tests 1 & 2	Theory part of the course	2	12
Exam	All Theory Part	2.5	40
Total		58.5	154

Learning Activities Summary

Lectures Activity	Session No.	Week	No of Lectures
Introduction to the course and presentation of prac structure	1&2	1	2
Introduction to fabrication processes, design rules (revisted). Transistor models (revisited from third year electronics) and layout issues and ASIC design flow	2&3	2	2
VLSI design methodology and leaf cell design	4&5	3	2
Performance estimation of CMOS complex gates and interconnected modules using logical effort	6-13	4-7	8
Interconnect issues, clock distribution, design margin, reliability and scaling	14-17	8,9	4
Static and dynamic CMOS logic families and adders design	18,19,20	10,11	2
Memory structures and operation	21,22	11,12	2
Low power design and system level consideration	23-24	12	2

Tutorials Activity	Sessions	Week	Topic
Demonstrating the design of CMOS gates and transistor sizing	1	2	Tutorial 1
CMOS circuits layout and delay estimation	2	4	Tutorial 2
CMOS circuits delay estimation using logical effort	3	6	Tutorial 3
Delay path estimation using logical effort	4	8	Tutorial 4
Delay and crosstalk in interconnects	5	10	Tutorial 5
PLA and memory Design	6	12	Tutorial 6

Practicals
Note that practical classes begin in week 1 of the semester and run in odd weeks. Students must attend their allocated practical class, when further instructions on the operation of the laboratory session will be provided. Students should be aware of the Occupational Health and Safety issues associated with working in a laboratory environment.

The University's policy on Assessment for Coursework Programs is based on the following four principles:

Assessment must encourage and reinforce learning.
Assessment must enable robust and fair judgements about student performance.
Assessment practices must be fair and equitable to students and give them the opportunity to demonstrate what they have learned.
Assessment must maintain academic standards.

Assessment Summary

Assessment Task	Task Type	Individual / Group	Due (week)*	Weighting	Hurdle Criteria	Learning Outcome
Computer Lab 1	Diagnostic	Individual	1 - 3	2%		2, 3, 9
Computer Lab 2	Diagnostic	Individual	4 - 6	3%		2, 3, 9
Computer Lab 3	Diagnostic	Individual	7 - 8	5%		2, 3, 4, 9
Computer Lab 4	Summataive	Group	9 - 13	25%		2, 3, 4, 5, 8, 9, 10
Tutorials	Formative	Individual	3, 5, 7, 9, 10, 11	10%		1 - 8
Test 1	Formative	Individual	7	5%		1 - 8
Test 2	Formative	Individual	12	5%		1 - 8
Exam	Summative	Individual	Exam period	45%	min 40%	1 - 8

* The specific due date for each assessment task will be available on MyUni.

This assessment breakdown complies with the University's Assessment for Coursework Programs Policy.

This course has a hurdle requirement. Meeting the specified hurdle criteria is a requirement for passing the course.

Online Tutorials:
Tutorials will be assessed and are worth 10% of the total assessment. The rationale behind this
is to reduce the weighing of the final Exam and use that as a continuous assessment. The aim of this approach is to reduce the pressure that some students may face when it come the final exam.

Practicals:
The practicals will be run in the computer labs. So, there is a need to attend these sessions to effectively use these labs, unless an unforeseen issue arises due to COVID-19, this arrangement might change.

Online Tests:
The tests assessment will run online. A number of questions will be provided to you through MyUni and you will be required to provide online answers to these questions, some of these might be numerical or require working, so you will also be required to submit your working by taking an image/scan of your work and do the submission online. Please get used for this form of interaction as this will also be used for the final examination.

Online Exam:
The plan for examinations is to be online, unless unforeseen issues arise that will require us to deviate from this approach. Again, similar to the tests, students will be required to submit scanned copies of their worked solutions during a timed session. The details for that will be provided in due date.

Assessment Detail

The examination is a hurdle requirement. It is necessary to achieve at least 40% in the exam. If this is not achieved, the total course mark will be limited to a maximum of 49.

A hurdle requirement is defined by the University's Assessment for Coursework Programs policy as "...an assessment task mandating a minimum level of performance as a condition of passing the course.If a student fails to meet a hurdle requirement (normally no less than 40%),and is assigned a total mark for the course in the range of 45-49, then the student is entitled to an offer of additional assessment of some type. The type of assessment is to be decided by the School Assessment Review Committee when determining final results. The student’s final total mark will be entered at no more than 49% and the offer of an additional assessment will be specified eg. US01. Once the additional assessment has been completed, this mark will be included in the calculation of the total mark for the course and the better of the two results will apply. Note however that the maximum final result for a course in which a student has sat an additional assessment will be a “50 Pass”.

If a student is unable to meet a hurdle requirement related to an assessment piece (may be throughout semester or at semester’s end) due to medical or compassionate circumstances beyond their control, then the student is entitled to an offer of replacement assessment of some type. An interim result of RP will be entered for the student, and the student will be notified of the offer of a replacement assessment. Once the replacement assessment has been completed, the result of that assessment will be included in the calculation of the total mark for the course.An assessment of work done during the lab will be conducted at the end of each lab session.

Submission

Submission will be through MyUni and information on the process will be provided for each assignment in due course.

Course Grading

Grades for your performance in this course will be awarded in accordance with the following scheme:

M10 (Coursework Mark Scheme)
Grade	Mark	Description
FNS		Fail No Submission
F	1-49	Fail
P	50-64	Pass
C	65-74	Credit
D	75-84	Distinction
HD	85-100	High Distinction
CN		Continuing
NFE		No Formal Examination
RP		Result Pending

Further details of the grades/results can be obtained from Examinations.

Grade Descriptors are available which provide a general guide to the standard of work that is expected at each grade level. More information at Assessment for Coursework Programs.

Final results for this course will be made available through .

Student Feedback

The University places a high priority on approaches to learning and teaching that enhance the student experience. Feedback is sought from students in a variety of ways including on-going engagement with staff, the use of online discussion boards and the use of Student Experience of Learning and Teaching (SELT) surveys as well as GOS surveys and Program reviews.

SELTs are an important source of information to inform individual teaching practice, decisions about teaching duties, and course and program curriculum design. They enable the University to assess how effectively its learning environments and teaching practices facilitate student engagement and learning outcomes. Under the current SELT Policy (http://www.adelaide.edu.au/policies/101/) course SELTs are mandated and must be conducted at the conclusion of each term/semester/trimester for every course offering. Feedback on issues raised through course SELT surveys is made available to enrolled students through various resources (e.g. MyUni). In addition aggregated course SELT data is available.
Student Support
Policies & Guidelines
This section contains links to relevant assessment-related policies and guidelines - all university policies.
Fraud Awareness

Students are reminded that in order to maintain the academic integrity of all programs and courses, the university has a zero-tolerance approach to students offering money or significant value goods or services to any staff member who is involved in their teaching or assessment. Students offering lecturers or tutors or professional staff anything more than a small token of appreciation is totally unacceptable, in any circumstances. Staff members are obliged to report all such incidents to their supervisor/manager, who will refer them for action under the university's student鈥檚 disciplinary procedures.

The 成人大片 is committed to regular reviews of the courses and programs it offers to students. The 成人大片 therefore reserves the right to discontinue or vary programs and courses without notice. Please read the important information contained in the disclaimer.

Authorised by:	Deputy Vice-Chancellor and Vice-President (Academic)
Maintained by:	Course Outlines Administrator

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